Final Test

FINAL TEST

Once the front-end process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%.

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data is logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test".

Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible, because many testers have the resources to perform most or all of the tests in parallel.

Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing, and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during the testing, in order to achieve tightly-distributed resistance values as specified by the design.

Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.

1. A method for final testing a lot consisting of a predetermined plurality of semiconductor devices, comprising the steps of: 

Testing operation of a test system relative to a predetermined set of test system performance characteristics; 

if said test system fails to operate in accordance with said predetermined set of test system performance characteristics, repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics; 

certifying that said test system is operating in accordance with said predetermined set of test system performance criteria; 

testing a plurality of semiconductor device performance characteristics of each of said lot of semiconductor devices with said test system, said testing resulting in passing semiconductor devices operating in accordance with said plurality of semiconductor device performance characteristics and failing semiconductor devices not operating in accordance with said plurality of semiconductor device performance characteristics;

subsequent to said testing of said lot of semiconductor devices, testing operation of said test system relative to said predetermined set of test system performance characteristics;

if said test system fails to operate in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices

repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics, following repair of said test system restarting testing each of said lot of semiconductor devices and subsequent to said restart of testing of said lot of semiconductor devices retesting operation of said test system;

if said test system operates in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices, recertifying that said test system is operating in accordance with said predetermined set of test system performance criteria; and packing and shipping said passing semiconductor devices.

2. The method according to claim 1, wherein said certifying step further comprises comparing a plurality of test system performance characteristics with a predetermined set of statistical rules.

3. The method according to claim 1, wherein said certifying step further comprises comparing a plurality of test system performance characteristics with a plurality of modified WECO rules.

4. The method according to claim 1, wherein at least one of said predetermined set of performance criteria is certified during said step of testing.

Research by : Adli