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This blog is created to show about all the TEST that involve making of microchip.

First of all, we would like to show to you a video that will make u feel excited to know more details about microchip.

This is the video on how to make a microchip.

Assembly Test

Assembly Test

      The assembly process is necessary to protect the chip, facilitate its integration into electronic systems, limit electrical interference and enable the dissipation of heat from the device. Once the front-end production process is complete, the wafer is transferred to an assembly facility, where it is sawed into individual semiconductor chips.

      These semiconductor chips are then individually attached by means of an alloy or an adhesive to a lead frame, a metallic device used to connect the semiconductor to a circuit board. Leads on the lead frame are then connected by aluminum or gold wires to the input/output terminals on the semiconductor chip through the use of automated machines known as wire bonders. Each semiconductor device is then encapsulated in a plastic molding compound or ceramic case, forming the package.

      After assembly, power semiconductors are tested for different operating specifications, including functionality, voltage, current and timing. The completed packages are then shipped to the customer or to their final end-user destination through drop shipment.

Research by: Amir

Wafer Test

Introduction

Wafer testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are probably the most common.

Wafer prober

8-inch semiconductor wafer prober, shown with cover panels, tester and probe card elements removed.

A wafer prober is a machine used to test integrated circuits. For electrical testing a set of microscopic contacts or probes called a probe card are held in place whilst the wafer, vacuum-mounted on a wafer chuck, is moved into electrical contact. When a die (or array of dice) have been electrically tested the prober moves the wafer to the next die (or array) and the next test can start. The wafer prober is usually responsible for loading and unloading the wafers from their carrier (or cassette) and is equipped with automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy to ensure accurate registration between the contact pads on the wafer and the tips of the probes.

For today’s multi-die packages such as stacked chip-scale package (SCSP) or System in Package (SiP) – the development of non-contact (RF) probes for identification of known tested die (KTD) and known good die (KGD) are critical to increasing overall system yield.

The wafer prober also exercises any test circuitry on the wafer scribe lines. Some companies get most of their information about device performance from these scribe line test structures.

When all test patterns pass for a specific die, its position is remembered for later use during IC packaging. Sometimes a die has internal spare resources available for repairing (i.e. flash memory IC); if it does not pass some test patterns these spare resources can be used. If redundancy of failed die is not possible the die is considered faulty and is discarded. Non-passing circuits are typically marked with a small dot of ink in the middle of the die, or the information of passing/non-passing is stored in a file, named a wafermap. This map categorizes the passing and non-passing dies by making use of bins. A bin is then defined as a good or bad die. This wafermap is then sent to the die attachment process which then only picks up the passing circuits by selecting the bin number of good dies. The process where no ink dot is used to mark the bad dies is named substrate mapping. When ink dots are used, vision systems on subsequent die handling equipment can disqualify the die by recognizing the ink dot.

In some very specific cases, a die that passes some but not all test patterns can still be used as a product, typically with limited functionality. The most common example of this is a microprocessor for which only one part of the on-die cache memory is functional. In this case, the processor can sometimes still be sold as a lower cost part with a smaller amount of memory and thus lower performance. Additionally when bad dies have been identified, the die from the bad bin can be used by production personnel for assembly line setup.

The contents of all test patterns and the sequence by which they are applied to an integrated circuit are called the test program.

After IC packaging, a packaged chip will be tested again during the IC testing phase, usually with the same or very similar test patterns. For this reason, one might think that wafer testing is an unnecessary, redundant step. In reality this is not usually the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when the production yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and dies will undergo blind assembly.

Research by: Shidi

Wafer Test Video

Failure Analysis Test

FAILURE ANALYSIS

Failure analysis is the process of collecting and analyzing data to determine the cause of a failure. It is an important discipline in many branches of manufacturing industry, such as the electronics industry, where it is a vital tool used in the development of new products and for the improvement of existing products. The failure analysis process relies on collecting failed components for subsequent examination of the cause or causes of failure using a wide array of methods, especially microscopy and spectroscopy.

Failure analysis engineers

A failure analysis engineer often plays a lead role in the analysis of failures, whether a component or product fails in service or if failure occurs in manufacturing or during production processing. In any case, one must determine the cause of failure to prevent future occurrence, and/or to improve the performance of the device, component or structure.

TECHNIQUES OF FAILURE ANALYSIS

This is a focused approach designed to include one or more specific analysis techniques to understand, characterize or determine a defined task/need.

level 1

The scope of the analysis includes failure verification, non-destructive examination of product, sub-system, or component and internal visual examination.

level 2

This stage of the investigation uses fault isolation techniques to localize the failure to a specific site on a sample, providing valuable information pointing to a design, product, or package issue.

level 3

The scope of this effort incorporates designing and applying the appropriate FA methodology to physically identify and characterize the failure mechanism and ultimately determine root cause.

level 4

The stage of failure analysis which digs deeper into the use of specialized techniques and tools for a full causal analysis. Examples include circuit modification followed by retest, Laser timing probe, nanoprobing, materials characterization, contamination and its definitive role in the failure. 

Research by : Hairi

Front-end and Back-end Test

Semiconductor Production Process: Front-end and Back-end

The semiconductor production process can be divided into two sequential sub-processes commonly referred to as front-end and back-end production, both of which contain many steps. The entire process, both front-end and back-end production, is complex and requires sophisticated engineering and manufacturing expertise. The diagram below summarizes the process.

Front-end production

Wafer Fabrication. Front-end production refers primarily to wafer fabrication. It starts with a clean disc-shaped silicon wafer that will ultimately become many silicon chips. First, a photomask that defines the circuit patterns for the transistors and interconnect layers is created. This mask is then laid on the clean silicon wafer and is used to map the circuit design. Transistors and other circuit elements are then formed on the wafer through photolithography. Photolithography involves a series of steps in which a photosensitive material is deposited on the wafer and exposed to light through a patterned mask; unwanted exposed material is then etched away, leaving only the desired circuit pattern on the wafer. By stacking the various patterns, individual elements of the semiconductor chip are defined. During the final phase of the front-end production process, each individual chip on the wafer is electrically tested to identify properly functioning chips for assembly.

Back-end production

Assembly and Test. Back-end production refers to the assembly and test of individual semiconductors. The assembly process is necessary to protect the chip, facilitate its integration into electronic systems, limit electrical interference and enable the dissipation of heat from the device. Once the front-end production process is complete, the wafer is transferred to an assembly facility, where it is sawed into individual semiconductor chips. These semiconductor chips are then individually attached by means of an alloy or an adhesive to a lead frame, a metallic device used to connect the semiconductor to a circuit board. Leads on the lead frame are then connected by aluminium or gold wires to the input/output terminals on the semiconductor chip through the use of automated machines known as wire bonders. Each semiconductor device is then encapsulated in a plastic molding compound or ceramic case, forming the package.

After assembly, power semiconductors are tested for different operating specifications, including functionality, voltage, current and timing. The completed packages are then shipped to the customer or to their final end-user destination through drop shipment.

Research by : Wan Aiman

Final Test

FINAL TEST

Once the front-end process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%.

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data is logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test".

Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible, because many testers have the resources to perform most or all of the tests in parallel.

Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing, and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during the testing, in order to achieve tightly-distributed resistance values as specified by the design.

Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.

1. A method for final testing a lot consisting of a predetermined plurality of semiconductor devices, comprising the steps of: 

Testing operation of a test system relative to a predetermined set of test system performance characteristics; 

if said test system fails to operate in accordance with said predetermined set of test system performance characteristics, repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics; 

certifying that said test system is operating in accordance with said predetermined set of test system performance criteria; 

testing a plurality of semiconductor device performance characteristics of each of said lot of semiconductor devices with said test system, said testing resulting in passing semiconductor devices operating in accordance with said plurality of semiconductor device performance characteristics and failing semiconductor devices not operating in accordance with said plurality of semiconductor device performance characteristics;

subsequent to said testing of said lot of semiconductor devices, testing operation of said test system relative to said predetermined set of test system performance characteristics;

if said test system fails to operate in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices

repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics, following repair of said test system restarting testing each of said lot of semiconductor devices and subsequent to said restart of testing of said lot of semiconductor devices retesting operation of said test system;

if said test system operates in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices, recertifying that said test system is operating in accordance with said predetermined set of test system performance criteria; and packing and shipping said passing semiconductor devices.

2. The method according to claim 1, wherein said certifying step further comprises comparing a plurality of test system performance characteristics with a predetermined set of statistical rules.

3. The method according to claim 1, wherein said certifying step further comprises comparing a plurality of test system performance characteristics with a plurality of modified WECO rules.

4. The method according to claim 1, wherein at least one of said predetermined set of performance criteria is certified during said step of testing.

Research by : Adli